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Lecture 8.2 | The Processor-Part2

:material-circle-edit-outline: 约 427 个字 :fontawesome-solid-code: 8 行代码 :material-clock-time-two-outline: 预计阅读时间 2 分钟

承接上节课的预测

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期中考试考到单周期，流水线不考

4.6 RISC-V Pipelined Datapath

单周期图划为五个区域，对应流水线的五个阶段

当然这不是最终的版本

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从右往左的线会造成hazard

左上角对应了控制冒险，这个mux决定下一条指令是pc+4还是跳转到imm对应的地址

右下角对应了数据冒险

Pipeline registers

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通过阶段之间的reg储存上一阶段的结果，方便下一阶段使用

IF for Load, Store, …

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ID for Load, Store, …

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EX for Load

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MEM for Load

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WB for Load

这张图有问题，地址是不对的

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Corrected Datapath for Load

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EX for Store

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Pipeline Operation

注意记一下两种diagram的名字

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Multi-Cycle Pipeline Diagram

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下图为简化画法，考试就用这种画就行

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Single-Cycle Pipeline Diagram

指令放最上面

注意是与muti-cycle相反，最上面这一行指令是从右往左顺序，即先运行ld x10, 40(x1)

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Pipelined Control

都要背下来

Pipelined Control (Simplified)

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没有考虑jal，不然太复杂了

4.7 Data Hazards

如何去解决data hazard，如何实现forwarding

Consider this sequence:

sub x2, x1,x3
and x12,x2,x5
or x13,x6,x2
add x14,x2,x2
sd x15,100(x2)

Dependencies & Forwarding

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Detecting the Need to Forward

  • Pass register numbers along pipeline
    • e.g., ID/EX.RegisterRs1 = register number for Rs1 sitting in ID/EX pipeline register
  • ALU operand register numbers in EX stage are given by
    • ID/EX.RegisterRs1, ID/EX.RegisterRs2

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  • But only if forwarding instruction will write to a register!
    • EX/MEM.RegWrite, MEM/WB.RegWrite
  • And only if Rd for that instruction is not x0
    • EX/MEM.RegisterRd ≠ 0, MEM/WB.RegisterRd ≠ 0

Forwarding Paths

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Forwarding Conditions

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Double Data Hazard

Consider the sequence

add x1,x1,x2
add x1,x1,x3
add x1,x1,x4

Revised Forwarding Condition

下面这个是描述hazard的语言，要学习，考试会考

不需要死记硬背

你会写黑的就会写蓝的

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Datapath with Forwarding

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Load-Use Hazard Detection

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How to Stall the Pipeline

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Load-Use Data Hazard

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Datapath with Hazard Detection

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Stalls and Performance

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4.8 Branch Hazards

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Reducing Branch Delay

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Example: Branch Taken

预测

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